During the testing of semiconductor wafers, it is often necessary to temporarily connect to semiconductor chip or chips, each containing a complex electronic circuit. This temporary contacting technology is described in detail in for example, U.S. Pat. Nos. 4,027,935 and 5,207,585 assigned to the same assignee as the present invention. These chips have small contact areas which are often connected to chip carriers having electrical conductors for carrying electrical signals between the chips. Contact is often made between these contact areas and the electrical conductors by using the so called C4 solder bump “flip-chip” technology.
Before an investment is made in joining the chips to the chip carrier, it is desirable to test the electrical functionality of each chip. Chips that do not meet test specifications can be discarded, rather than an entire assembly of chips and the chip carrier. In order to do this testing, the very small contact areas on the chip must be connected to a test apparatus. This is typically done at the wafer level.
Typically the contact areas on the chips are impacted by small contact areas of a probing device during test. The difficulty is that the closely spaced pins of the probe must be attached to the more widely spaced lands on a printed circuit board, in order to conduct electrical signals between the test apparatus and the chip having the contact areas that have been contacted by the pins of the probe. This is essentially a fan-out problem.
At least two approaches have been used in an attempt to solve this problem. One makes use of a multilayered ceramic or laminate substrate for the fan-out to the printed circuit board. The main problem with this technique is the lead time; custom designs require additional costs and time to manufacture. From the viewpoint of high frequency, alternating current performance, this approach is better than a second approach noted below.
A second approach uses a hand wired fan-out apparatus made essentially by fabricating a guide template which is a copy of the chip footprint. The wires are manually routed to the printed circuit board. A principal difficulty with this approach is that AC performance of such a hand wired apparatus is very limited, principally because of the unshielded nature of the wires.